The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having bonding pads and micro-bonding pads. The bonding pads and micro-bonding pads may be small electrical contacts formed on the surface of an integrated circuit and used for joining multiple integrated circuits in a three-dimensional package.
New integrated circuit (IC) technologies may include individual IC chips (i.e., “dies”) arranged into a three-dimensional integrated circuit, also known as a three-dimensional semiconductor package (3D package). One type of 3D package can include two or more layers of active electronic components stacked vertically and electrically joined with some combination of through-substrate vias and solder bumps. The 3D package can provide numerous benefits such as increased package density yielding a smaller footprint, and improved bandwidth due to the short connection lengths between the individual dies.
One example of a 3D package may include a die stack and a laminate substrate. The die stack may include at least two die or IC chips. The die may be stacked on top of one another, and electrically and mechanically joined using a combination of through-substrate vias (TSVs) and a first plurality of solder connections (i.e., Controlled Collapse Chip Connections (C4), flip chip connections). The TSVs can drastically reduce interconnect distance as compared to other typical interconnect methods, such as, for example, wire bonding. The small interconnect distances may enable faster communication speeds, may lower power consumption, and may ultimately reduce the overall package size. The dies may contain devices with small feature sizes, including processor devices, which may require smaller connection points, so micro-solder bumps having a much smaller pitch than traditional solder bumps may be used.
The die stack may further be electrically and mechanically joined to the laminate substrate using a second plurality of solder bump connections. Generally, the second plurality of solder connections between the laminate substrate and the die stack are larger than the first plurality of solder bump connections between successive die in the die stack. Therefore, the second plurality of solder connections may be fewer in quantity with a greater pitch or spacing than the first plurality of second bump connections. The second plurality of solder connections may have a pitch of approximately 185 μm.